Large scale integration techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multi-component circuits in a conventional bistable configuration. There are numerous advantages of such semiconductor storage devices including high packing density and low power requirements of such memory cells.
Numerous prior art static cells of an integrated circuit memory have been developed. A well known static memory cell circuit arrangement which utilizes six insulated gate MOS field-effect transistors is a cross-coupled inverter stage shown in U.S. Pat. No. 3,967,252 issued to Donnelly on June 29, 1976 and entitled "Sense Amp for Random Access Memory". In that arrangement, in an effort to minimize the area required for a given number of memory cells, there are two cross-coupled inverters comprising two load devices and four transistors, such that a single cell includes six transistors. In an attempt to further reduce the dimensions of the cell structure of integrated circuit memories and to provide improved performance and higher packing densities, a structural layout in which four transistors and two resistive elements has been developed and is described in U.S. Pat. No. 4,125,854 issued to McKenney et al on Nov. 14, 1978 and entitled "Symmetrical Cell Layout for Static RAM".
In order to further improve upon the layout area and power drain of static memory devices, pseudo-static random access memories have been proposed using a one-transistor, one-capacitor dynamic cell together with self-refreshing circuitry. A self-refreshing cell utilizing five transistors and dynamic sensing is described in a paper by Caywood et al entitled "A Novel 4K Static RAM with Submilliwatt Standby Power", IEEE Transactions on Electron Devices, Volume ED.-26, No. 6, June, 1979 at page 861. However, the high packing density desired in such memory cells cannot be achieved using five transistors. A charge pumping loop utilizing a two-device inverter is described in a paper by Cilingiroglu entitled "A Charge-Pumping-Loop Concept for Static MOS/RAM Cells", IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 3, June, 1979, at page 599. Transistor and resistor charge pumping loops as described suffer in that the storage of a logic "1" is degraded and the control of cell resistor values is difficult. Since these pseudo-static cells are derived from the one-transistor, one-capacitor dynamic cell concept, their readout is inherently destructive and must be refreshed after each read. Therefore, pseudo-static cells are not truly compatible with fully static memory operation. Furthermore, since pseudo-static cells store information on a capacitor without a holding device, they are sensitive to alpha-particle induced errors.
A need has thus arisen for a static MOS memory cell in which the number and area of cell components are minimized to increase packing densities in semiconductor storage devices. A need has further arisen for a static memory cell which can be read in a nondestructive manner resulting in a fully static memory operation. Additionally, a need has arisen for a semiconductor storage device having low power requirements while operating at high speeds. A need has further arisen for a semiconductor storage device having improved alpha-particle immunity and in which fabrication controls are minimal.